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ST72104Gx-Auto, ST72215GX-AUTO, ST72216Gx-Auto, ST72254Gx-Auto
8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, I2C interfaces

Memories - 4K or 8K bytes Program memory (ROM and single voltage Flash) with readout protection and in-situ programming (remote ISP) - 256 bytes RAM Clock, Reset and Supply Management - Enhanced reset system - Enhanced low voltage supply supervisor with 3 programmable levels - Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System - Clock-out capability - 3 Power Saving Modes: Halt, Wait and Slow Interrupt Management - 7 interrupt vectors plus TRAP and RESET - 22 external interrupt lines (on 2 vectors) 22 I/O Ports - 22 multifunctional bidirectional I/O lines - 14 alternate function lines - 8 high sink outputs 3 Timers - Configurable watchdog timer - Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes (one only on ST72104Gx-Auto and ST72216G1Auto)
SO28

2 Communications Interfaces - SPI synchronous serial interface - I2C multimaster interface (only on ST72254Gx-Auto) 1 Analog Peripheral - 8-bit ADC with 6 input channels (except on ST72104Gx-Auto) Instruction Set - 8-bit data manipulation - 63 basic instructions - 17 main addressing modes - 8 x 8 unsigned multiply instruction - True bit manipulation Development Tools - Full hardware/software development package
Device Summary
ST72104G1- ST72104G2- ST72216G1- ST72215G2- ST72254G1- ST72254G2Auto Auto Auto Auto Auto Auto Program memory Flash/ROM 4 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes RAM (stack) 256 (128) bytes Watchdog timer One 16-bit timer Two 16-bit timers Peripherals SPI ADC I2C Operating Supply 3.2V to 5.5 V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) Operating Temperature -40C to +85C / -40C to +105C / -40C to +125C Packages SO28 Features
Rev. 1
October 2007 1/135
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 4.3 4.4 4.5 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STRUCTURAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MEMORY READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 5.3 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 20 20 20 21 22 22 22 22 23 6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 6.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Safe Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 6.6
CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 NON-MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 7.3 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 8.3 8.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 33 9.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135. ... 9.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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9.4 9.5 9.6 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.6 Summary of Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 40 40 40 40 42 42 42 42 54 54 54 55 60 60 60 60 62 69 69 70 73 73 73 73 75 79 79 80 85 85 85 85 86 86 87
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12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 90 90 90 90 91 91 92
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.1.1 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 Loading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.5 Pin Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 95 95 95 95 96 96 96 96 97
13.3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13.3.2 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 99 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 13.4.1 RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 WAIT and SLOW WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.5 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 102 103 103 103 104 104 104 105 108 109 110
13.6.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.6.2 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 13.7.1 Functional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.2 Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7.3 ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 112 114 116
13.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 116 ... 13.8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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13.9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.9.2 ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.10.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.10.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 123 13.11.1 SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.11.2 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.2 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 14.3 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 129 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 130 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 15.3.1 Package/Socket Footprint Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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1 INTRODUCTION
The ST72104G-Auto, ST72215G-Auto, ST72216G-Auto and ST72254G-Auto devices are members of the ST7 microcontroller family. They can be grouped as follows: - ST72254G-Auto devices are designed for midrange applications with ADC and IC interface capabilities. - ST72215/6G-Auto devices target the same range of applications but without IC interface. - ST72104G-Auto devices are for applications that do not need ADC and IC peripherals. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72C104G, ST72C215G, ST72C216G and ST72C254G versions feature single-voltage Flash Figure 1. General Block Diagram memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, all devices can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in Section 13 on page 95.
OSC1 OSC2
MULTI OSC + CLOCK FILTER LVD
INTERNAL CLOCK I2C PORT A PA7:0 (8 bits)
VDD VSS RESET
POWER SUPPLY
SPI
ADDRESS AND DATA BUS
PORT B 16-BIT TIMER A PORT C 8-BIT ADC 16-BIT TIMER B
PB7:0 (8 bits)
CONTROL 8-BIT CORE ALU
PROGRAM MEMORY (4 or 8K bytes)
PC5:0 (6 bits)
RAM (256 bytes)
WATCHDOG
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2 PIN DESCRIPTION
Figure 2. 28-Pin SO Package Pinout
RESET OSC1 OSC2 SS/PB7 ISPCLK/SCK/PB6 ISPDATA/MISO/PB5 MOSI/PB4 OCMP2_A/PB3 ICAP2_A/PB2 OCMP1_A/PB1 ICAP1_A/PB0 AIN5/EXTCLK_A/PC5 AIN4/OCMP2_B/PC4 AIN3/ICAP2_B/PC3 VDD VSS ISPSEL PA0 (HS) PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS)/SCLI PA5 (HS) PA6 (HS)/SDAI PA7 (HS) PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/MCO/AIN2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 ei1 ei0
28 27 26 25 24 23 22 21 20 19 18 17 ei0 or ei1 16 15
(HS) 20mA high sink capability eiX associated external interrupt vector
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PIN DESCRIPTION (Cont'd) For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 95. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: - Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog - Output: OD = open drain 2), PP = push-pull Refer to Section 9 "I/O PORTS" on page 30 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. SO28 Device Pin Description
Pin Type No. 1 2 3 4 5 6 7 8 9 RESET OSC1 3) OSC2 3) PB7/SS PB6/SCK/ISPCLK Name Level Output Input float Port / Control Input Output wpu ana OD PP int Main Function (after reset)
Alternate Function
I/O CT I O I/O I/O CT CT CT CT CT CT CT CT CT CT CT CT CT CT X X X X X X X X
X
X
Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator
ei1 ei1 ei1 ei1 ei1 ei1 ei1 ei1
X X X X X X X X X X X X X X
X X X X X X X X X X X X X X
Port B7 Port B6 Port B5 Port B4 Port B3 Port B2 Port B1 Port B0 Port C5 Port C4 Port C3 Port C2 Port C1 Port C0
SPI Slave Select (active low) SPI Serial Clock or ISP Clock SPI Master In/ Slave Out Data or ISP Data SPI Master Out / Slave In Data Timer A Output Compare 2 Timer A Input Capture 2 Timer A Output Compare 1 Timer A Input Capture 1 Timer A Input Clock or ADC Analog Input 5 Timer B Output Compare 2 or ADC Analog Input 4 Timer B Input Capture 2 or ADC Analog Input 3 Main clock output (fCPU) or ADC Analog Input 2 Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0
PB5/MISO/ISPDATA I/O PB4/MOSI PB3/OCMP2_A PB2/ICAP2_A I/O I/O I/O I/O I/O
10 PB1 /OCMP1_A 11 PB0 /ICAP1_A
12 PC5/EXTCLK_A/AIN5 I/O 13 PC4/OCMP2_B/AIN4 I/O 14 PC3/ ICAP2_B/AIN3 15 PC2/MCO/AIN2 I/O I/O
X ei0/ei1 X ei0/ei1 X ei0/ei1 X X ei0/ei1 X X ei0/ei1 X X ei0/ei1 X
16 PC1/OCMP1_B/AIN1 I/O 17 PC0/ICAP1_B/AIN0 I/O
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Pin Type No. 18 PA7 19 PA6 /SDAI 20 PA5 21 PA4 /SCLI 22 PA3 23 PA2 24 PA1 25 PA0 26 ISPSEL 27 VSS 28 VDD Name
Level Output Input float
Port / Control Input Output wpu ana OD PP int
Main Function (after reset) Port A7 Port A6
Alternate Function
I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O CT HS I/O CT HS I S S C
X X X X X X X X X
ei0 ei0 ei0 ei0 ei0 ei0 ei0 ei0
X T X T X X X X
X
I2C Data I2C Clock
X
Port A5 Port A4
X X X X
Port A3 Port A2 Port A1 Port A0 In-situ programming selection (should be tied low in standard user mode). Ground Main power supply
Notes: 1. In the interrupt input column, "eiX" defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 30 and Section 13.8 "I/O PORT PIN CHARACTERISTICS" on page 116 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 7 and Section 13.5 "CLOCK AND TIMING CHARACTERISTICS" on page 104 for more details.
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3 REGISTER AND MEMORY MAP
As shown in the Figure 3, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. Figure 3. Memory Map IMPORTANT: Memory locations marked as "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
0000h 007Fh 0080h
HW Registers (see Table 2)
0080h
256 bytes RAM
017Fh 0180h
00FFh 0100h
Short Addressing RAM Zero page (128 bytes) Stack or 16-bit Addressing RAM (128 bytes)
Reserved
DFFFh E000h
017Fh
Program Memory (4K, 8K bytes)
FFDFh FFE0h FFFFh
E000h
8 Kbytes
F000h
Interrupt & Reset Vectors (see Table 5 on page 26)
4 Kbytes
FFFFh
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Table 2. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh to 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh to 0030h I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR SPI WATCHDOG MISCR1 SPIDR SPICR SPISR WDGCR CRSR Port A PADR PADDR PAOR Port B PBDR PBDDR PBOR Block Register Label PCDR PCDDR PCOR Register Name Port C Data Register Port C Data Direction Register Port C Option Register Reserved (1 byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved (1 byte) Port A Data Register Port A Data Direction Register Port A Option Register Reserved (21 bytes) Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register 00h xxh 0xh 00h 7Fh R/W R/W R/W Read Only R/W 00h 1) 00h 00h R/W R/W R/W 00h 1) 00h 00h R/W R/W R/W Reset Status 00h 1) 00h 00h Remarks R/W 2) R/W 2) R/W 2)
Port C
Clock, Reset, Supply Control / Status Register 000x 000x R/W Reserved (2 bytes) Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register Reserved (2 bytes) 00h 00h 00h 00h 00h 00h 00h R/W Read Only Read Only R/W R/W R/W R/W
I2C
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Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h to 006Fh 0070h 0071h 0072h to 007Fh
Block
Register Label TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR
Register Name Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register Miscellaneous Register 2 Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register Reserved (32 bytes)
Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h
Remarks R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W
TIMER A
TIMER B
ADC
ADCDR ADCCSR
Data Register Control/Status Register Reserved (14 bytes)
00h 00h
Read Only R/W
Legend: x=undefined, R/W=read/write
Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value.
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4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION Flash devices have a single voltage non-volatile Flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by-byte basis. 4.2 MAIN FEATURES

Remote In-Situ Programming (ISP) mode Up to 16 bytes programmed in the same cycle MTP memory (Multiple Time Programmable) Readout memory protection against piracy
4.3 STRUCTURAL ORGANIZATION The Flash program memory is organized in a single 8-bit wide memory block which can be used for storing both code and data constants. The Flash program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area. 4.4 IN-SITU PROGRAMMING (ISP) MODE The Flash program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implemented with a minimum number of added components and board area impact. An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification. Remote ISP Overview The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin. The Remote ISP is performed in three steps: - Selection of the RAM execution mode - Download of Remote ISP code in RAM - Execution of Remote ISP code in RAM to program the user program into the Flash Remote ISP hardware configuration In Remote ISP mode, the ST7 has to be supplied with power (VDD and VSS) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the VDD signal if necessary) to be connected to the programming tool. This signals are: - RESET: device reset - VSS: device ground power supply - ISPCLK: ISP output serial clock pin - ISPDATA: ISP input serial data pin - ISPSEL: Remote ISP mode selection. This pin must be connected to VSS on the application board through a pull-down resistor. If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level. Figure 4 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description. Figure 4. Typical Remote ISP Interface XTAL
HE10 CONNECTOR TYPE TO PROGRAMMING TOOL
1 CL0 CL1
OSC2
OSC1
VDD
ISPSEL 10K VSS RESET
ST7
ISPCLK ISPDATA 47K
APPLICATION
4.5 MEMORY READOUT PROTECTION The readout protection is enabled through an option bit. For Flash devices, when this option is selected, the program and data stored in the Flash memory are protected against readout piracy (including a re-write protection). When this protection option is removed the entire Flash program memory is first automatically erased. However, the E2PROM data memory (when available) can be protected only with ROM devices.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES

63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt
5.3 CPU REGISTERS The six CPU registers shown in Figure 5 are not present in the memory mapping and are accessed by specific instructions. Figure 5. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0
Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value
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CPU REGISTERS (cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
7 1 1 1 H I N Z 0 C
because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions.
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible
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CPU REGISTERS (cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh
15 0 7 0 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 6). Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 6. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 6. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 017Fh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72104G-Auto, ST72215G-Auto, ST72216G-Auto and ST72254G-Auto microcontrollers include a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 7. See Section 13 "ELECTRICAL CHARACTERISTICS" on page 95 for more details. Main Features Supply Manager with main supply low voltage detection (LVD) Reset Sequence Manager (RSM) Multi-Oscillator (MO) - 4 Crystal/Ceramic resonator oscillators - 1 External RC oscillator - 1 Internal RC oscillator Clock Security System (CSS) - Clock Filter - Backup Safe Oscillator Figure 7. Clock, Reset and Supply Block Diagram
MCO CLOCK SECURITY SYSTEM (CSS) OSC2 OSC1 MULTIOSCILLATOR (MO) CLOCK FILTER SAFE OSC fOSC MAIN CLOCK CONTROLLER (MCC) fCPU
RESET
RESET SEQUENCE MANAGER (RSM)
FROM WATCHDOG PERIPHERAL
VDD VSS
LOW VOLTAGE DETECTOR (LVD)
LVD CRSR 0 0 0 RF 0
CSS IE D
WDG RF
CSS INTERRUPT
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6.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in the Figure 8. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the MCU can only be in two modes: - under full software control - in static safe reset Figure 8. Low Voltage Detector vs Reset VDD In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: 1. The LVD allows the device to be used without any external RESET circuitry. 2. Three different reference levels are selectable through the option byte according to the application requirement. LVD application note Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register. This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
Vhyst VIT+ VIT-
RESET
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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 10: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of three phases as shown in Figure 9: Delay depending on the RESET source 4096 CPU clock cycle delay RESET vector fetch Figure 10. Reset Block Diagram The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 9. RESET Sequence Phases
RESET
DELAY INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR
VDD
fCPU
COUNTER
INTERNAL RESET
RON
RESET
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 11). Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 11. RESET Sequences VDD
VIT+ VIT-
6.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: Power-On RESET Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDLVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
DELAY
RUN
DELAY
RUN
DELAY
RUN
DELAY
RUN
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
th(RSTL)in
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (4096 TCPU) FETCH VECTOR
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6.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: an external source 4 crystal or ceramic resonator oscillators an external RC oscillator an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 3. Refer to the electrical characteristics section for more details. External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. External RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is dependent on VDD, TA, process variations and the accuracy of the discrete components used. This option should not be used in applications that require accurate timing. Internal RC Oscillator The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz. This option should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Table 3. ST7 Clock Sources
Hardware Configuration
External Clock
ST7 OSC1 OSC2
EXTERNAL SOURCE
Crystal/Ceramic Resonators
ST7 OSC1 OSC2
CL1
LOAD CAPACITORS
ST7 OSC1 OSC2
CL2
External RC Oscillator
REX
CEX
Internal RC Oscillator
ST7 OSC1 OSC2
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6.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. 6.4.1 Clock Filter Control The clock filter is based on a clock frequency limitation function. This filter function is able to detect and filter high frequency spikes on the ST7 main clock. If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock. 6.4.2 Safe Oscillator Control The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 12). If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations. Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers. Limitation detection The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CSSIE bit has been previously set. These two bits are described in the CRSR register description. 6.4.3 Low Power Modes
Mode WAIT Description No effect on CSS. CSS interrupt cause the device to exit from Wait mode. The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET.
HALT
6.4.4 Interrupts The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event Enable Event Control Flag Bit CSSIE Exit from Wait Yes Exit from Halt1) No
CSS event detection (safe oscillator acti- CSSD vated as main clock)
Notes: 1. This interrupt allows to exit from Active Halt mode if this mode is available in the MCU.
Figure 12. Clock Filter Function and Safe Oscillator Function
CLOCK FILTER FUNCTION
fOSC/2 fCPU
SAFE OSCILLATOR FUNCTION
fOSC/2 fSFOSC fCPU
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6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) Read / Write Reset Value: 000x 000x (XXh)
7 0 0 0 LVD RF 0 CSS IE 0 CSS WDG D RF
Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined. Bit 3 = Reserved, always read as 0. Bit 2 = CSSIE Clock security syst. interrupt enable This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software. 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled Refer to Table 5, "Interrupt Mapping," on page 26 for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.
Bit 1 = CSSD Clock security system detection This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (fOSC). It is set by hardware and cleared by reading the CRSR register when the original oscillator recovers. 0: Safe oscillator is not active 1: Safe oscillator has been activated When the CSS is disabled by option byte, the CSSD bit value is forced to 0. Bit 0 = WDGRF Watchdog reset flag This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table.
RESET Sources External RESET pin Watchdog LVD LVDRF 0 0 1 WDGRF 0 1 X
Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset cannot.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address (Hex.) 0025h Register Label CRSR Reset Value 7 6 5 4 LVDRF x 3 2 CSSIE 0 1 CSSD 0 0 WDGRF x
0
0
0
0
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6.6 MAIN CLOCK CONTROLLER (MCC) The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be managed by the application. All functions are managed by the Miscellaneous register 1 (MISCR1). The MCC block consists of: A programmable CPU clock prescaler A clock-out signal to supply external devices The prescaler allows the selection of the main clock frequency and is controlled by three bits of the MISCR1: CP1, CP0 and SMS. The clock-out capability consists of a dedicated I/O port pin configurable as an fCPU clock output to drive external devices. It is controlled by the MCO bit in the MISCR1 register. See Section 10 "MISCELLANEOUS REGISTERS" on page 36 for more details.
Figure 13. Main Clock Controller (MCC) Block Diagram
CLOCK TO CAN PERIPHERAL PORT ALTERNATE FUNCTION fOSC/2 MISCR1 MCO CP1 CP0 SMS
MCO
fOSC
DIV 2
DIV 2, 4, 8, 16 fCPU
CPU CLOCK TO CPU AND PERIPHERALS
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7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 14. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 7.1 NON-MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 14. 7.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 7.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) Figure 14. Interrupt Processing Flowchart
FROM RESET I BIT SET? Y N
N
INTERRUPT PENDING? Y
FETCH NEXT INSTRUCTION
N
IRET? Y
STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
No. Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: 1. Configurable by option byte. IC TIMER B ei0 ei1 CSS SPI TIMER A Reset Software Interrupt External Interrupt Port A7..0 (C5..01) External Interrupt Port B7..0 (C5..01) Clock Security System Interrupt SPI Peripheral Interrupts TIMER A Peripheral Interrupts Not used TIMER B Peripheral Interrupts Not used Not used Not used Not used IC Peripheral Interrupt Not Used Not Used I2CSRx Lowest Priority no TBSR no CRSR SPISR TASR no N/A Description Register Label Priority Order Highest Priority Exit from HALT yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 15). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. Figure 15. Power Saving Mode Transitions
High RUN
fCPU
8.2 SLOW MODE This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency. Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode. Figure 16. SLOW Mode Clock Transitions
fOSC/4 fOSC/8 fOSC/2
SLOW
fOSC/2 MISCR1
WAIT SLOW WAIT HALT Low POWER CONSUMPTION
CP1:0 SMS
00
01
NEW SLOW FREQUENCY REQUEST
NORMAL RUN MODE REQUEST
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POWER SAVING MODES (Cont'd) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 17. Figure 17. WAIT Mode Flowchart
OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0
WFI INSTRUCTION
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 1 Y
4096 CPU CLOCK CYCLE DELAY
OSCILLATOR PERIPHERALS CPU I BIT
ON ON ON X 1)
FETCH RESET VECTOR OR SERVICE INTERRUPT Notes: 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.4 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 19). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 5, "Interrupt Mapping," on page 26) or a RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 18). When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the "WDGHALT" option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 15.1 "OPTION BYTES" on page 129 for more details). Figure 18. HALT Mode Timing Overview
4096 CPU CYCLE DELAY
Figure 19. HALT Mode Flow-chart
HALT INSTRUCTION ENABLE WDGHALT 1) 1 WATCHDOG RESET OSCILLATOR OFF PERIPHERALS 2) OFF CPU OFF I BIT 0 0 WATCHDOG DISABLE
N RESET N Y INTERRUPT 3) Y OSCILLATOR PERIPHERALS CPU I BIT ON OFF ON 1
4096 CPU CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS CPU I BIT ON ON ON X 4)
RUN
HALT
RUN
FETCH RESET VECTOR OR SERVICE INTERRUPT Notes: 1. WDGHALT is an option bit. See option byte section for more details. 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to Table 5, "Interrupt Mapping," on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
HALT INSTRUCTION
RESET OR INTERRUPT
FETCH VECTOR
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9 I/O PORTS
9.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has two main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 20. 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 21). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 9.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain VSS Floating
9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 20. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 0 ALTERNATE ENABLE DR
VDD
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 6. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
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I/O PORTS (Cont'd) Table 7. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. Warning: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 21. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Table 8. Port Configuration
Input (DDR = 0) Port Pin name OR = 0 PA7 PA6 PA5 PA4 PA3:0 PB7:0 PC7:0 floating floating floating floating floating floating floating OR = 1
Figure 21. Interrupt I/O Port State Transitions
01 00 10 OUTPUT open-drain 11 OUTPUT push-pull
INPUT INPUT floating/pull-up floating interrupt (reset state)
XX = DDR, OR
The I/O port register configurations are summarized as follows. Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
True Open Drain Interrupt Ports PA6, PA4 (without pull-up)
MODE floating input floating interrupt input open drain (high sink ports) DDR 0 0 1 OR 0 1 X
Output (DDR = 1) OR = 0 OR = 1 High-Sink
Port A
Port B Port C
pull-up interrupt floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up interrupt pull-up interrupt
open drain push-pull true open-drain open drain push-pull true open-drain open drain push-pull open drain push-pull open drain push-pull
Yes
No
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I/O PORTS (Cont'd) 9.4 LOW POWER MODES
Mode WAIT HALT Description No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 0 DD6 DD5 DD4 DD3 DD2 DD1 DD0
9.5 INTERRUPTS The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
Interrupt Event External interrupt on selected external event Enable Event Control Flag Bit DDRx ORx Exit from Wait Yes Exit from Halt Yes DD7
Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
9.6 REGISTER DESCRIPTION DATA REGISTER (DR) Port x Data Register PxDR with x = A, B or C. Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behavior according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).
Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Pull-up input with or without interrupt Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull (when available)
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I/O PORTS (Cont'd) Table 9. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Reset Value of all I/O port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah PCDR PCDDR PCOR PBDR PBDDR PBOR PADR PADDR PAOR
MSB
LSB
MSB
LSB
MSB
LSB
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10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions. 10.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE. This control allows having two fully independent external interrupt source sensitivities with configurable sources (using EXTIT option bit) as shown in Figure 22 and Figure 23. Each external interrupt source can be generated on four different events on the pin: Falling edge Rising edge Falling and rising edge Falling edge and low level To guarantee correct functionality, the sensitivity bits in the MISCR1 register must be modified only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming. 10.2 I/O PORT ALTERNATE FUNCTIONS The MISCR registers manage four I/O port miscellaneous alternate functions: Main clock signal (fCPU) output on PC2 SPI pin configuration: - SS pin internal control to use the PB7 I/O port function while the SPI is active. - Master output capability on MOSI pin (PB4) deactivated while the SPI is active. - Slave output capability on MISO pin (PB5) deactivated while the SPI is active. These functions are described in detail in the Section 10.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 37.
PA0 MISCR1 ei1 INTERRUPT SOURCE IS10 IS11
Figure 22. Ext. Interrupt Sensitivity (EXTIT=0)
PA7 ei0 INTERRUPT SOURCE
MISCR1 IS00 IS01
PA0 PC5
SENSITIVITY CONTROL
PC0 MISCR1 ei1 INTERRUPT SOURCE IS10 IS11
PB7
SENSITIVITY CONTROL
PB0
Figure 23. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1 ei0 INTERRUPT SOURCE IS00 IS01
PA7
SENSITIVITY CONTROL
PB7
PB0 PC5
SENSITIVITY CONTROL
PC0
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MISCELLANEOUS REGISTERS (Cont'd) 10.3 MISCELLANEOUS REGISTER DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MCO IS01 IS00 CP1 CP0 0 fCPU in SLOW mode SMS fOSC / 4 fOSC / 8 fOSC / 16 CP1 0 1 0 1 CP0 0 0 1 1
Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
Bit 7:6 = IS1[1:0] ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei1: Port B (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS11 IS10 0 0 1 1 0 1 0 1
fOSC / 32
Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.
Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Bit 4:3 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei0: Port A (C optional)
External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge IS01 IS00 0 0 1 1 0 1 0 1
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 MOD SOD SSM 0 SSI
Bit 7:4 = Reserved always read as 0 Bit 3 = MOD SPI Master Output Disable This bit is set and cleared by software. When set, it disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled. Bit 2 = SOD SPI Slave Output Disable This bit is set and cleared by software. When set it disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled. Bit 1 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode, the level of the SPI SS signal is read from the SSI bit. Bit 0 = SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 7 IS11 0 0 6 IS10 0 0 5 MCO 0 0 4 IS01 0 0 3 IS00 0 MOD 0 2 CP1 0 SOD 0 1 CP0 0 SSM 0 0 SMS 0 SSI 0
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features Programmable timer (64 increments of 12288 CPU cycles) Programmable reset Reset (if watchdog activated) when the T6 bit reaches zero Optional reset on HALT instruction (configurable by option byte) Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the RESET pin for typically 30s. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset.
Figure 24. Watchdog Block Diagram
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /12288
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WATCHDOG TIMER (Cont'd) Table 11. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.4 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte description. 11.1.5 Low Power Modes WAIT Instruction No effect on Watchdog. HALT Instruction If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes an immediate reset generation if the Watchdog is activated (WDGA bit is set). 11.1.5.1 Using Halt Mode with the WDG (option) If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state). Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
- When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as "Input Pull-up with Interrupt" before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. - For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure. - The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 11.1.6 Interrupts None. 11.1.7 Register Description CONTROL REGISTER (CR) Read / Write Reset Value: 0111 1111 (7F h)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
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WATCHDOG TIMER (Cont'd) Table 12. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0024h Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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11.2 16-BIT TIMER 11.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 11.2.2 Main Features Programmable prescaler: fCPU divided by 2, 4 or 8. Overflow status flag and maskable interrupt External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt Pulse Width Modulation mode (PWM) One Pulse mode 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 25. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout description. When reading an input signal on a non-bonded pin, the value will always be `1'. 11.2.3 Functional Description 11.2.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR) - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 13 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 25. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 low 8-bit buffer EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 16 INPUT CAPTURE REGISTER 2 16 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8
8 high
OUTPUT COMPARE CIRCUIT 6
EDGE DETECT CIRCUIT1
ICAP1 pin
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Clearing the overflow interrupt request is done in two steps: 1.Reading the SR register while the TOF bit is set. 2.An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 11.2.3.2 External Clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 26. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 27. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 28. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 11.2.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see Figure 29).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 30). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The two input capture functions can be used together even if the timer also uses the two output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 29. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 30. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 11.2.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
= Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) = Timer prescaler factor (2, 4 or 8 dePRESC pending on CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 32 on page 50). This behavior is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 33 on page 50). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 31. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit
OC1E OC2E
CC1
CC0
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 32. Output Compare Timing Diagram, fTIMER = fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 33. Output Compare Timing Diagram, fTIMER = fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 11.2.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 13 Clock Control Bits).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 34). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin cannot be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 34. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 35. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1 OLVL2
2ED0 2ED1 2ED2
34E2
FFFC
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
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16-BIT TIMER (Cont'd) 11.2.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1 = 0 and OLVL2 = 1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). If OLVL1 = 1 and OLVL2 = 0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. Pulse Width Modulation cycle When Counter = OC1R
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 35) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin cannot be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 11.2.4 Low Power Modes
Mode WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Description
HALT
11.2.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 11.2.6 Summary of Timer Modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode Input Capture 1 Yes Yes No No AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes Not recommended1) No Partially 2) Not recommended3) No No
Notes: 1. See note 4 in Section 11.2.3.5 "One Pulse Mode" on page 51. 2. See note 5 in Section 11.2.3.5 "One Pulse Mode" on page 51. 3. See note 4 in Section 11.2.3.6 "Pulse Width Modulation Mode" on page 53.
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16-BIT TIMER (Cont'd) 11.2.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 13. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2:0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 14. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Register Label 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 5 TOIE 0 OPM 0 TOF 0 4 FOLV2 0 PWM 0 ICF2 0 3 FOLV1 0 CC1 0 OCF2 0 2 OLVL2 0 CC0 0 0 1 IEDG1 0 IEDG2 0 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
Timer A: 32 CR1 Timer B: 42 Reset Value Timer A: 31 CR2 Timer B: 41 Reset Value Timer A: 33 SR Timer B: 43 Reset Value Timer A: 34 ICHR1 Timer B: 44 Reset Value Timer A: 35 ICLR1 Timer B: 45 Reset Value Timer A: 36 OCHR1 Timer B: 46 Reset Value Timer A: 37 OCLR1 Timer B: 47 Reset Value Timer A: 3E OCHR2 Timer B: 4E Reset Value Timer A: 3F OCLR2 Timer B: 4F Reset Value Timer A: 38 CHR Timer B: 48 Reset Value Timer A: 39 CLR Timer B: 49 Reset Value Timer A: 3A ACHR Timer B: 4A Reset Value Timer A: 3B ACLR Timer B: 4B Reset Value Timer A: 3C ICHR2 Timer B: 4C Reset Value Timer A: 3D ICLR2 Timer B: 4D Reset Value
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1 -
1 -
1 -
1 -
1 -
0 -
-
-
-
-
-
-
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11.3 SERIAL PERIPHERAL INTERFACE (SPI) 11.3.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pinout. 11.3.2 Main Features Full duplex, three-wire synchronous transfers Master or slave operation 4 master mode frequencies Maximum slave mode frequency = fCPU/4 4 programmable master bit rates Programmable clock polarity and phase End of transfer interrupt flag Write collision flag protection Master mode fault protection capability 11.3.3 General description The SPI is connected to external devices through four alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 36. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 39) but master and slave must be programmed with the same timing mode.
Figure 36. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK
SCK +5V
SS
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 37. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer DR IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL
SR MODF -
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4 Functional Description Figure 36 shows the serial peripheral interface (SPI) block diagram. This interface contains three dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 11.3.7 for the bit definitions. 11.3.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 and SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 39). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input.
Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 39. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2. A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 11.3.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 11.3.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 39, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device. The master device applies data to its MOSI pinclock edge before the capture clock edge. Figure 38. CPHA / SS Timing Diagram
CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 38). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 38). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 39. Data Clock Timing Diagram
CPHA =1
SCLK (with CPOL = 1) SCLK (with CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: A "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 40).
Figure 40. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing to the DR register instead of reading in it does not reset the WCOL bit.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit cannot be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multimaster conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 11.3.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: For more security, the slave device may respond to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR regisSingle Master System ter. A typical single master system may be configured, Other transmission security methods can use using an MCU as the master and four MCUs as ports for handshake lines or data bytes with comslaves (see Figure 41). mand fields. The master device selects the individual slave deMultimaster System vices by using four pins of a parallel port to control the four SS pins of the slave devices. A multimaster system may also be configured by the user. Transfer of master control could be imThe SS pins are pulled high during reset since the plemented using a handshake method through the master device ports will be forced to be inputs at I/O ports or by an exchange of code messages that time, thus disabling the slave devices. through the serial peripheral interface system. Note: To prevent a bus conflict on the MISO line The multi-master system is principally handled by the master allows only one active slave device the MSTR bit in the CR register and the MODF bit during a transmission. in the SR register. Figure 41. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.5 Low Power Modes
Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
11.3.6 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.3.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
7 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 15. Serial Peripheral Baud Rate
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.3.4.5 "Master Mode Fault" on page 67). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 15. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.3.4.5 "Master Mode Fault" on page 67). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128
SPR2 1 0 0 1 0 0
SPR1 0 0 0 1 1 1
SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 40). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.3.4.5 "Master Mode Fault" on page 67). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3:0 = Unused.
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 37).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 16. SPI Register Map and Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPISR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x 0
x SPE 0 WCOL 0
x SPR2 0 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x 0
x SPR1 x 0
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11.4 I2C BUS INTERFACE (I2C) 11.4.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz). 11.4.2 Main Features 2 Parallel-bus/I C protocol converter Multi-master capability 7-bit/10-bit Addressing Transmitter/Receiver flag End-of-byte transmission flag Transfer problem detection I2C Master Features Clock generation 2 I C bus busy flag Arbitration Lost Flag End of byte transmission flag Transmitter/Receiver Flag Start bit detection flag Start and Stop generation I2C Slave Features Stop bit detection 2 I C bus busy flag Detection of misplaced start or stop condition 2 Programmable I C Address detection Transfer problem detection End-of-byte transmission flag Transmitter/Receiver flag 11.4.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled Figure 42. I2C BUS Protocol SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION ACK handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: - Slave transmitter/receiver - Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 42.
VR02119B
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I2C BUS INTERFACE (Cont'd) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100 kHz) and Fast I2C (up to 400 kHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. Figure 43. I2C Interface Block Diagram
The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I / O port pins.
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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I2C BUS INTERFACE (Cont'd) 11.4.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 11.4.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 11.4.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: - Acknowledge pulse if the ACK bit is set. - EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 44 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set - EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 44 Transfer sequencing EV2). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 44 Transfer sequencing EV3). When the acknowledge pulse is received: - The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: - EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 44 Transfer sequencing EV4). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. Note: In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set at the same time.
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I2C BUS INTERFACE (Cont'd) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus Compatibility ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I2C Peripheral. 11.4.4.2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 44 Transfer sequencing EV5). Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 44 Transfer sequencing EV9).
Then the second address byte is sent by the interface. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 44 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set - EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 44 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
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I2C BUS INTERFACE (Cont'd) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 44 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first pulse of each 9-bit transaction: Single Master Mode If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle of communication gives the possibility to reinitiate transmis-
sion. Multimaster Mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. - ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set at the same time.
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I2C BUS INTERFACE (Cont'd) Figure 44. Transfer Sequencing 7-bit Slave receiver:
S Address A EV1 Data1 A EV2 Data2 A EV2 ..... DataN A EV2 P EV4
7-bit Slave transmitter:
S Address A EV1 EV3 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3-1 P EV4
7-bit Master receiver:
S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN NA EV7 P
7-bit Master transmitter:
S EV5 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P
10-bit Slave receiver:
S Header A Address A EV1 Data1 A EV2 ..... DataN A EV2 P EV4
10-bit Slave transmitter:
Sr Header A EV1 EV3 Data1 A .... DataN EV3 . A EV3-1 P EV4
10-bit Master transmitter
S EV5 Header A EV9 Address A EV6 EV8 Data1 A EV8 ..... DataN A EV8 P
10-bit Master receiver:
Sr EV5 Header A EV6 Data1 A EV7 ..... DataN A EV7 P
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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I2C BUS INTERFACE (Cont'd) 11.4.5 Low Power Modes
Mode WAIT HALT Description No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
11.4.6 Interrupts Figure 45. Event Flags and Interrupt Generation
ADD10 BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT
EVF
* * EVF can also be set by EV6 or an error from the SR2 register.
Event Flag ADD10 BTF ADSL SB AF STOPF ARLO BERR Enable Control Bit Exit from Wait Yes Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No No
Interrupt Event 10-bit Address Sent Event (Master mode) End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event
ITE
Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
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I2C BUS INTERFACE (Cont'd) 11.4.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 PE 0 ENGC START ACK STOP ITE
- In slave mode: 0: No start generation 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). - In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. - In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 45 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 44) is detected.
Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: - When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). - In master mode: 0: No start generation 1: Repeated start generation
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I2C BUS INTERFACE (Cont'd) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)
7 EVF ADD10 TRA BUSY BTF ADSL M/SL 0 SB
tection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus 1: Communication ongoing on the bus Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 44). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 44. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - ADSL=1 (Address matched in Slave mode while ACK=1) - SB=1 (Start condition generated in Master mode) - AF=1 (No acknowledge received after byte transmission) - STOPF=1 (Stop condition detected in Slave mode) - ARLO=1 (Arbitration lost in Master mode) - BERR=1 (Bus error, misplaced Start or Stop condition detected) - ADD10=1 (Master has sent header byte) - Address byte successfully transmitted in Master mode. Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after de-
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I2C BUS INTERFACE (Cont'd) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated I2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h)
7 0 0 0 AF 0 STOPF ARLO BERR GCAL
Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Note: - In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Note: - If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus
Bit 7:5 = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. 0: No acknowledge failure 1: Acknowledge failure Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected
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I2C BUS INTERFACE (Cont'd) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)
7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 CC0
I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h)
7 0
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC[6:0] 7-bit clock divider. These bits select the speed of the bus (fSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). Refer to the Electrical Characteristics section for the table of values. Note: The programmed fSCL assumes no load on SCL and SDA lines. I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don't care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. 10-bit Addressing Mode Bit 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). I2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h)
7 FR1 FR0 0 0 0 ADD9 ADD8 0 0
Bit 7:0 = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. - Transmitter mode: Byte transmission start automatically when the software writes in the DR register. - Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
Bit 7:6 = FR[1:0] Frequency bits. These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I2C specified delays select the value corresponding to the microcontroller frequency fCPU.
fCPU < 6 MHz 6 to 8 MHz FR1 0 0 FR0 0 1
Bit 5:3 = Reserved Bit 2:1 = ADD[9:8] Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0 = Reserved.
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Table 17. I2C Register Map and Reset Values
Address (Hex.) 0028h 0029h 002Ah 02Bh 02Ch 002Dh 002Eh Register Label I2CCR Reset Value I2CSR1 Reset Value I2CSR2 Reset Value I2CCCR Reset Value I2COAR1 Reset Value I2COAR2 Reset Value I2CDR Reset Value 7 6 5 PE 0 TRA 0 0 CC5 0 ADD5 0 0 0 4 ENGC 0 BUSY 0 AF 0 CC4 0 ADD4 0 0 0 3 START 0 BTF 0 STOPF 0 CC3 0 ADD3 0 0 0 2 ACK 0 ADSL 0 ARLO 0 CC2 0 ADD2 0 ADD9 0 0 1 STOP 0 M/SL 0 BERR 0 CC1 0 ADD1 0 ADD8 0 0 0 ITE 0 SB 0 GCAL 0 CC0 0 ADD0 0 0 LSB 0
0 EVF 0 0 FM/SM 0 ADD7 0 FR1 0 MSB 0
0 ADD10 0 0 CC6 0 ADD6 0 FR0 1 0
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11.5 8-BIT A/D CONVERTER (ADC) 11.5.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is an 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pinout description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in an 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 11.5.2 Main Features 8-bit conversion Up to 16 channels with multiplexed input Linear successive approximation Data register (DR) which contains the results Conversion complete status flag On/off bit (to reduce consumption) The block diagram is shown in Figure 46. Figure 46. ADC Block Diagram 11.5.3 Functional Description 11.5.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pinout description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details.
fCPU
DIV 2
fADC
COCO
0
ADON
0
CH3 CH2
CH1 CH0
ADCCSR
4
AIN0 AIN1 RADC
HOLD CONTROL
ANALOG MUX
AINx CADC
ANALOG TO DIGITAL CONVERTER
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
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8-BIT A/D CONVERTER (ADC) (Cont'd) 11.5.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time. 11.5.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases as shown in Figure 47: Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 11.5.3.4 Software Procedure Refer to the control/status register (CSR) and data register (DR) in Section 11.5.6 for the bit definitions and to Figure 47 for the timings. ADC Configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=2/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the "I/O ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH[3:0] bits to assign the analog channel to be converted. ADC Conversion In the CSR register: - Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 47. ADC Conversion Timings
ADON tCONV
ADCCSR WRITE OPERATION
HOLD CONTROL
tLOAD
COCO BIT SET
11.5.4 Low Power Modes
Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wake-up from Halt mode, the A/D Converter requires a stabilization time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.5.5 Interrupts None
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8-BIT A/D CONVERTER (ADC) (Cont'd) 11.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h)
7 COCO 0 ADON 0 CH3 CH2 CH1 0 CH0
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag.
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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8-BIT A/D CONVERTER (ADC) (Cont'd) Table 18. ADC Register Map and Reset Values
Address (Hex.) 0070h 0071h Register Label ADCDR Reset Value ADCCSR Reset Value 7 D7 0 COCO 0 6 D6 0 0 5 D5 0 ADON 0 4 D4 0 0 3 D3 0 CH3 0 2 D2 0 CH2 0 1 D1 0 CH1 0 0 D0 0 CH0 0
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12 INSTRUCTION SET
12.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 19. ST7 Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax
so, most of the addressing modes may be subdivided in two submodes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination/ Source
Pointer Address (Hex.)
Pointer Size (Hex.) +0 +1
Length (bytes)
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+1271) PC-128/PC+1271) 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
btjt [$10],#7,skip 00..FF
Notes: 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont'd) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
12.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indexed addressing mode consists of three submodes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
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ST7 ADDRESSING MODES (Cont'd) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two submodes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 20. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function
12.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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12.2 INSTRUCTION GROUPS The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a prebyte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C
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INSTRUCTION GROUPS (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt
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13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 13.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 13.1.2 Typical Values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range) and VDD=3.3V (for the 3VVDD4V voltage range). They are given only as design guidelines and are not tested. 13.1.3 Typical Curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading Capacitor The loading conditions used for pin parameter measurement are shown in Figure 48. Figure 48. Pin Loading Conditions 13.1.5 Pin Input Voltage The input voltage measurement on a pin of the device is described in Figure 49. Figure 49. Pin Input Voltage
ST7 PIN
VIN
ST7 PIN
CL
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13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics
Symbol VDD - VSS VIN 1) & 2) VESD(HBM) VESD(MM) Supply voltage Input voltage on true open drain pin Input voltage on any other pin Electrostatic discharge voltage (Human Body Model) Electrostatic discharge voltage (Machine Model) Ratings
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Maximum value 6.5 VSS-0.3 to 6.5 VSS-0.3 to VDD+0.3
Unit V
see Section 13.7.2 "Absolute Electrical Sensitivity" on page 112
13.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) Total current out of VSS ground lines (sink)
3) 3)
Maximum value 80 80 25 50 - 25 5 5 5 5 20
5) & 6)
Unit
Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on ISPSEL pin IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other pin IINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5)
mA
13.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Value -65 to +150 Unit C
Maximum junction temperature (see Section 14.3 "THERMAL CHARACTERISTICS" on page 128)
Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN96/135
ST72104Gx-Auto, ST72215GX-AUTO, ST72216Gx-Auto, ST72254Gx-Auto
13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions
Symbol VDD fOSC Parameter Supply voltage External clock frequency Conditions see Figure 50 and Figure 51 VDD3.5V for ROM devices VDD4.5V for Flash devices VDD3.2V Suffix A version TA Ambient temperature range Suffix B version Suffix C version -40 Min 3.2 0 1) Max 5.5 16 8 +85 +105 +125 C Unit V MHz
Figure 50. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for ROM Devices 2)
fOSC [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 8 4 1 0 2.5 3.2 3.5 3.85 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1)
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OPERATING CONDITIONS (Cont'd) Figure 51. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for Flash devices 2)
fOSC [MHz] FUNCTIONALITY NOT GUARANTEED IN THIS AREA AT TA > 85C
FUNCTIONALITY GUARANTEED IN THIS AREA 3)
16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 12 8 4 1 0 2.5 3.2 3.5 3.85 4 4.5 5 5.5 SUPPLY VOLTAGE [V] FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR 1)
Notes: 1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz. 2. Operating conditions with TA=-40 to +125C. 3. Flash programming tested in production at maximum TA with two different conditions: VDD=5.5V, fCPU=8MHz and VDD=3.2V, fCPU=4MHz.
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OPERATING CONDITIONS (Cont'd) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fOSC, and TA.
Symbol VIT+ Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis VDD rise time rate 3) Filtered glitch delay on VDD 2) Conditions High Threshold Med. Threshold Low Threshold High Threshold Med. Threshold Low Threshold4) VIT+-VITNot detected by the LVD Min 4.10 2) 3.75 2) 3.25 2) 3.85 2) 3.50 2) 3.00 200 0.2 Typ 1) 4.30 3.90 3.35 4.05 3.65 3.10 250 Max 4.50 4.05 3.55 4.30 3.95 3.35 300 50 40 Unit
V
VITVhyst VtPOR tg(VDD)
mV V/ms ns
Figure 52. High LVD Threshold Versus VDD and fOSC for Flash devices 3)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 12 8 0 2.5 3 3.5 VIT-3.85 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
Figure 53. Medium LVD Threshold Versus VDD and fOSC for Flash devices 3)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 12 8 0 2.5 3 FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
VIT-3.5V
Figure 54. Low LVD Threshold Versus VDD and fOSC for Flash devices 2)4)
fOSC [MHz] 16 12 DEVICE UNDER RESET IN THIS AREA 8 SEE NOTE 4 0 2.5 VIT-3V 3.2 SUPPLY VOLTAGE [V] 3.5 4 4.5 5 5.5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85C FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA
Notes: 1. LVD typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. Data based on characterization results, not tested in production. 3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. 4. If the low LVD threshold is selected, when VDD falls below 3.2V, (VDD minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified VDD min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level.
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FUNCTIONAL OPERATING CONDITIONS (Cont'd) Figure 55. High LVD Threshold Versus VDD and fOSC for ROM devices 2)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 2.5 3 3.5 VIT-3.85 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
Figure 56. Medium LVD Threshold Versus VDD and fOSC for ROM devices 2)
fOSC [MHz] DEVICE UNDER RESET IN THIS AREA 16 8 0 2.5 3 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 4 4.5 5 5.5
VIT-3.5V
Figure 57. Low LVD Threshold Versus VDD and fOSC for ROM devices 2)3)
fOSC [MHz] 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 FUNCTIONALITY NOT GUARANTEED IN THIS AREA FUNCTIONAL AREA SUPPLY VOLTAGE [V] 3.5 4 4.5 5 5.5
VIT-3.00V
Notes: 1. LVD typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production. 3. If the low LVD threshold is selected, when VDD falls below 3.2V, the device is guaranteed to be either functioning or under reset.
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13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total deSymbol IDD(Ta) Parameter Supply current variation vs. temperature
vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
Conditions Constant VDD and fCPU Max 10 Unit %
13.4.1 RUN and SLOW Modes
Symbol Parameter Supply current in RUN mode 3) (see Figure 58) Supply current in SLOW mode 4) (see Figure 59) IDD Supply current in RUN mode 3) (see Figure 58) Supply current in SLOW mode 4) (see Figure 59) 3.2VVDD3.6V 4.5VVDD5.5V Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz Typ 1) 500 1500 5600 150 250 670 300 970 3600 100 170 420 Max 2) 900 2500 9000 450 550 1250 550 1350 4500 250 300 700 Unit
A
Figure 58. Typical IDD in RUN vs. fCPU
IDD [mA] 7 8MHz 6 5 4MHz 2MHz 500kHz
Figure 59. Typical IDD in SLOW vs. fCPU
IDD [mA] 0.8 0.7 0.6 0.5 500kHz 250kHz 125kHz 31.25kHz
4
0.4
3
0.3
2 1 0 3.2 3.5 4 4.5 5 5.5 VDD [V]
0.2 0.1 0 3.2 3.5 4 4.5 5 5.5 VDD [V]
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.4V (3.2VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter Supply current in WAIT mode (see Figure 60)
3)
3.2VVDD3.6V 4.5VVDD5.5V
Conditions fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz fOSC=1MHz, fCPU=500kHz fOSC=4MHz, fCPU=2MHz fOSC=16MHz, fCPU=8MHz fOSC=1MHz, fCPU=31.25kHz fOSC=4MHz, fCPU=125kHz fOSC=16MHz, fCPU=500kHz
Typ 1) 150 560 2200 20 90 340 90 350 1370 10 50 200
Max 2) 280 900 3000 70 190 850 200 550 1900 20 80 350
Unit
Supply current in SLOW WAIT mode 4) (see Figure 61) IDD Supply current in WAIT mode 3) (see Figure 60) Supply current in SLOW WAIT mode 4) (see Figure 61)
A
Figure 60. Typical IDD in WAIT vs. fCPU
IDD [mA] 3 8MHz 4MHz 2.5 2MHz 500kHz
Figure 61. Typical IDD in SLOW-WAIT vs. fCPU
IDD [mA] 0.35 0.3 0.25 500kHz 250kHz 125kHz 31.25kHz
2 0.2 1.5 0.15 1 0.1 0.5 0.05 0 3.2 3.5 4 4.5 5 5.5 3.2 3.5 4 4.5 5 5.5 VDD [V] VDD [V]
0
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.5VVDD5.5V range) and VDD=3.4V (3.2VVDD3.6V range). 2. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled. 4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.3 HALT Mode
Symbol Parameter Supply current in HALT mode 2) Conditions -40CTA+85C VDD=5.5V -40CTA+125C -40CTA+85C VDD=3.6V -40CTA+125C Typ 1) Max 10 150 6 100 Unit
IDD
-
A
13.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock
Symbol Parameter Supply current of internal RC oscillator Supply current of external RC oscillator 4) IDD(CK)
source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions Typ 1) 500 525 200 300 450 700 150 HALT mode 100 Max 3) 750 750 400 550 750 1000 350 150 A Unit
LP: Low power oscillator 4) & 5) MP: Medium power oscillator Supply current of resonator oscillator MS: Medium speed oscillator HS: High speed oscillator Clock security system supply current LVD supply current
IDD(LVD)
13.4.5 On-Chip Peripherals
Symbol IDD(TIM) IDD(SPI) IDD(I2C) IDD(ADC) Parameter 16-bit Timer supply current 6) SPI supply current 7) I2C supply current 8) ADC supply current when converting 9) Conditions VDD=3.4V fCPU=8MHz VDD=5.0V VDD=3.4V fCPU=8MHz VDD=5.0V VDD=3.4V fCPU=8MHz VDD=5.0V VDD=3.4V fADC=4MHz VDD=5.0V Typ 50 150 250 350 250 350 800 1100 Unit
A
Notes: 1. Typical data are based on TA=25C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on characterization results, tested in production at VDD max. and fCPU max. 3. Data based on characterization results, not tested in production. 4. Data based on characterization results done with the external components specified in Section 13.5.3 and Section 13.5.4, not tested in production. 5. As the oscillator is based on a current source, the consumption does not depend on the voltage. 6. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 7. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communication (data sent equal to 55h). 8. Data based on a differential IDD measurement between reset configuration and I2C peripheral enabled (PE bit set). 9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
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13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 3 375
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
13.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) OSCx Input leakage current VSSVINVDD Conditions Min 0.7xVDD VSS 15 ns 15 1 A Typ Max VDD 0.3xVDD Unit V
see Figure 62
Figure 62. Typical Application with an External Clock Source
90% VOSC1H 10%
VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2
Not connected internally fOSC
EXTERNAL CLOCK SOURCE
OSC1
IL ST72XXX
Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 13.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as
Symbol fOSC RF CL1 CL2 Parameter Oscillator Frequency 3) Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (RS)
close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Min 1 >2 >4 >8 20 38 32 18 15 40 110 180 400 Max 2 4 8 16 40 56 46 26 21 100 190 360 700 Unit MHz k pF
Conditions LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator RS=200LP oscillator RS=200MP oscillator RS=200MS oscillator RS=100HS oscillator VDD=5VLP oscillator VIN=VSSMP oscillator MS oscillator HS oscillator
i2
OSC2 driving current
A
13.5.3.1 Typical Crystal Resonators
Option Byte Configuration LP MP MS HS JAUCH Reference S-200-30-30/50 SS3-400-30-30/30 SS3-800-30-30/30 Freq. Characteristic 1) CL1 CL2 tSU(osc) [pF] [pF] [ms] 2) 33 33 33 33 34 34 34 34 10~15 7~10 2.5~3 1~1.5
2MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=200 4MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=60
8MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=25 SS3-1600-30-30/30 16MHz fOSC=[30ppm25C,30ppmTa], Typ. RS=15
Figure 63. Typical Application with a Crystal Resonator
i2
fOSC OSC1
CL1
RESONATOR CL2 OSC2
RF ST72XXX
Notes: 1. Resonator characteristics given by the crystal manufacturer. 2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (<50s). 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to crystal manufacturer for more details.
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) 13.5.3.2 Typical Ceramic Resonators
Symbol Parameter Conditions LP 2MHz MP 4MHz MS 8MHz HS 16MHz Typ 4.2 2.1 1.1 0.7 Unit
tSU(osc)
Ceramic resonator start-up time
ms
tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (<50s). Table 21. Typical Ceramic Resonators for Automotive Applications
Option Byte Config. fOSC (MHz) 1 LP 2 2 MP 4 4 MS 8 8 10 HS 12 Resonator Part Number1) CSB1000JA CSBF1000JA CSTS0200MGA06 CSTCC2.00MGA0H6 CSTS0200MGA06 CSTCC2.00MGA0H6 CSTS0400MGA06 CSTCC4.00MGA0H6 CSTS0400MGA06 CSTCC4.00MGA0H6 CSTS0800MGA06 CSTCC8.00MGA0H6 CSTS0800MGA06 CSTCC8.00MGA0H6 CSTS1000MGA03 CSTCC10.0MGA CST12.0MTWA CSTCS12.0MTA CSA16.00MXZA040 162) CST16.00MXWA0C3 CSACV16.00MXA040Q CSTCV16.00MXA0H3Q Notes: 1. Murata Ceralock (refer to Table 22 for correlation factor) 2. VDD 4.5 to 5.5V 3. Values in parentheses refer to the capacitors integrated in the resonator (15) 30 (30) 15 (15) 15 (15) (15) 30 (30) 15 (15) 15 (15) 10 (47) (47) Open 0 CL1 [pF]3) 100 CL2 [pF]3) 100 RFEXT [k] RD [k] 3.3
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CLOCK AND TIMING CHARACTERISTICS (Cont'd) Figure 64. Typical Application with Ceramic Resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
i2
fOSC OSC1 RESONATOR
CL1
RF(EXT)
CL2 OSC2
RF ST72XXX
RD Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a quick VDD ramp-up from 0 to 5V (<50s). 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value. Refer to ceramic resonator manufacturer for more details.
Table 22. Ceramic Resonator Frequency Correlation Factor1)
Option Byte Configuration LP Resonator1) CSB1000J CSTS0200MG06 CSTCC2.00MG0H6 CSTS0200MG06 MP CSTCC2.00MG0H6 CSTS0400MG06 CSTS0400MGA06 CSTCC4.00MG0H6 CSTS0200MG06 CSTCC2.00MG0H6 CSTS0400MG06 CSTS0400MGA06 CSTCC4.00MG0H6 CSTS0200MG06 CSTS0800MG06 CSTS0800MGA06 CSTCC8.00MG0H6 CSTS1000MG03 CSTCC10.0MG CST12.0MTW CSTCV12.0MTJ0C4 CSTCS12.0MTA CSA16.00MXZ040 CSACV16.00MXJ040 CSACW1600MX03 CSACV16.00MXA040Q Correlation % +0.03 -0.16 -0.10 -0.15 -0.14 0.00 -0.01 -0.02 -0.15 -0.14 0.00 -0.01 -0.02 -0.15 +0.10 +0.07 +0.09 +0.34 +0.75 +0.45 +0.30 +0.50 +0.10 +0.09 +0.03 +0.09 Reference IC 4069UBE
74HCU04
MS
74HCU04
74HCU04 4069UBP 4069UBE 4069UBE 40H004 4069UBE
HS
74HCU04
Notes: 1. See Table 21 for ceramic resonator values.
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CLOCK CHARACTERISTICS (Cont'd) 13.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal
Symbol fOSC Parameter Internal RC oscillator frequency 1) External RC oscillator frequency 2) Internal RC oscillator start-up time 3) External RC oscillator start-up time 3) Oscillator external resistor 4) Oscillator external capacitor
or external components (selectable by option byte).
Min 3.60 1 Typ Max 5.10 14 Unit MHz
Conditions see Figure 66
tSU(OSC)
REX = 47K, CEX = "0"pF REX = 47K, CEX = 100pF REX = 10K, CEX = 6.8pF REX = 10K, CEX = 470pF see Figure 67 10 0 5)
2.0 1.0 6.5 0.7 3.0 47 470
ms
REX CEX
K pF
Figure 65. Typical Application with RC oscillator
ST72XXX
INTERNAL RC VDD
Current copy
EXTERNAL RC REX OSC1
VREF
+ -
fOSC
CEX
OSC2
Voltage generator
CEX discharge
Figure 66. Typical Internal RC Oscillator
fosc [MHz] 4.3 4.2 4.1 4 3.9 3.8 3.2 VDD [V] 5.5 -40C +25C +85C +125C
Figure 67. Typical External RC Oscillator
fosc [MHz] 20 15 10 5 0 0 6.8 22 47 Cex [pF] 100 270 470 Rex=10KOhm Rex=15KOhm Rex=22KOhm Rex=33KOhm Rex=39KOhm Rex=47KOhm
Notes: 1. Data based on characterization results. 2. Guaranteed frequency range with the specified CEX and REX ranges taking into account the device process variation. Data based on design simulation. 3. Data based on characterization results done with VDD nominal at 5V, not tested in production. 4. REX must have a positive temperature coefficient (ppm/C), carbon resistors should therefore not be used. 5. Important: When no external CEX is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by trying out several resistor values.
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CLOCK CHARACTERISTICS (Cont'd) 13.5.5 Clock Security System (CSS)
Symbol fSFOSC fGFOSC Parameter Safe Oscillator Frequency 1) Glitch Filtered Frequency 2) Conditions TA=25C, VDD=5.0V TA=25C, VDD=3.4V Min 250 190 Typ 340 260 30 Max 550 450 Unit kHz MHz
Figure 68. Typical Safe Oscillator Frequencies
fosc [kHz] 400 350 300 -40C +25C +85C +125C
250 200 3.2 VDD [V] 5.5
Notes: 1. Data based on characterization results, tested in production between 90 kHz and 600 kHz. 2. Filtered glitch on the fOSC signal. See functional description in Section 6.5 on page 23 for more details.
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13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 13.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 1.6
Typ
Max
Unit V
13.6.2 Flash Program Memory
Symbol TA(prog) tprog tret NRW Parameter Programming temperature range 2) Programming time for 1~16 bytes 3) Programming time for 4 or 8Kbytes Data retention 5) Write erase cycles 5) Conditions TA=+25C TA=+25C TA=+55C 4) TA=+25C Min 0 Typ 25 8 2.1 Max 70 25 6.4 Unit C ms sec years cycles
20 100
Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Data based on characterization results, tested in production at TA=25C. 3. Up to 16 bytes can be programmed at a time for a 4 Kbyte Flash block (then up to 32 bytes at a time for an 8 Kbyte device) 4. The data retention time increases when the TA decreases. 5. Data based on reliability test results and monitored in production.
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13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electromagnetic Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed.
Symbol VFESD VFFTB
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a functional disturbance
Conditions VDD=5V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-2 VDD=5V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-4
Neg 1) -1 -4
Pos 1) 1
Unit
kV 4
Figure 69. EMC Recommended star network power supply connection 2)
ST72XXX 10F 0.1F
ST7 DIGITAL NOISE FILTERING
VDD
VSS
VDD
POWER SUPPLY SOURCE
VSSA
EXTERNAL NOISE FILTERING
VDDA 0.1F
Notes: 1. Data based on characterization results, not tested in production. 2. The suggested 10F and 0.1F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
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EMC CHARACTERISTICS (Cont'd) 13.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 13.7.2.1 Electrostatic Discharge (ESD) Electrostatic Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). Two models are usually simulated: Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard. See Figure 70 and the following test sequences. Human Body Model Test Sequence - CL is loaded through S1 by the HV pulse generator. - S1 switches position from generator to R. - A discharge from CL through R (body resistance) to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. Absolute Maximum Ratings
Symbol VESD(HBM) VESD(MM) Ratings Electrostatic discharge voltage (Human Body Model) Electrostatic discharge voltage (Machine Model)
Machine Model Test Sequence - CL is loaded through S1 by the HV pulse generator. - S1 switches position from generator to ST7. - A discharge from CL to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse. - R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Conditions TA=+25C TA=+25C
Maximum value 1) Unit 2000 V 200
Figure 70. Typical Equivalent ESD Circuits
S1 R=1500 S1 R=10k~10M
HIGH VOLTAGE PULSE GENERATOR
CL=100pF
ST7
S2
HIGH VOLTAGE PULSE GENERATOR CL=200pF
ST7
S2
HUMAN BODY MODEL
MACHINE MODEL
Notes: 1. Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 13.7.2.2 Static and Dynamic Latch-Up LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note.
DLU: Electrostatic Discharges (one positive then one negative test) are applied to each pin of three samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 71. For more details, refer to the AN1181 ST7 application note.
Class 1) A A A
Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class TA=+25C TA=+85C VDD=5.5V, fOSC=4MHz, TA=+25C Conditions
Figure 71. Simplified Diagram of the ESD Generator for DLU
RCH=50M RD=330
DISCHARGE TIP
VDD VSS
CS=150pF ESD GENERATOR 2)
HV RELAY
ST7
DISCHARGE RETURN CONNECTION
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger.
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EMC CHARACTERISTICS (Cont'd) 13.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electrostatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 72 and Figure 73 for standard pins and in Figure 74 and Figure 75 for true open drain pins.
Standard Pin Protection To protect the output structure the following elements are added: - A diode to VDD (3a) and a diode from VSS (3b) - A protection device between VDD and VSS (4) To protect the input structure the following elements are added: - A resistor in series with the pad (1) - A diode to VDD (2a) and a diode from VSS (2b) - A protection device between VDD and VSS (4)
Figure 72. Positive Stress on a Standard Pad vs. VSS
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path Path to avoid
(3b) (2b)
VSS
VSS
Figure 73. Negative Stress on a Standard Pad vs. VDD
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path
(3b) (2b)
VSS
VSS
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EMC CHARACTERISTICS (Cont'd) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to VDD are not implemented. An additional local protection between the pad and VSS (5a & 5b) is implemented to completely absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, VSSA, ...) and power supply (VDD, VDDA, ...) are available for any reason (better noise immunity...), the structure shown in Figure 76 is implemented to protect the device against ESD.
Figure 74. Positive Stress on a True Open Drain Pad vs. VSS
VDD VDD
Main path Path to avoid
(1) OUT (4) IN
(5a)
(3b)
(2b)
(5b)
VSS
VSS
Figure 75. Negative Stress on a True Open Drain Pad vs. VDD
VDD VDD
Main path
(1) OUT (4) IN
(3b)
(3b)
(2b)
(3b)
VSS
VSS
Figure 76. Multisupply Configuration
VDD VDDA
VDDA
VSS
BACK TO BACK DIODE BETWEEN GROUNDS
VSSA
VSSA
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13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Input leakage current Static current consumption 4) Weak pull-up equivalent resistor 5) I/O pin capacitance Output high to low level fall time 6) External interrupt pulse time 7) CL=50pF Output low to high level rise time 6) Between 10% and 90% VSSVINVDD Floating input mode VIN=VSS VDD=5V VDD=3.4V
400 1 200 62 170 120 200 5 25 25 1 250 300
A k pF ns tCPU
Figure 77. Two typical Applications with unused I/O Pin
VDD 10k
ST72XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST72XXX
Figure 78. Typical IPU vs. VDD with VIN=VSS
Ipu [A] 70 60 50 40 30 20 10 0 3.2 3.5 4 Vdd [V] 4.5 5 5.5 Ta=-40C Ta=25C Ta=85C Ta=125C
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 77). Data based on design simulation and/or technology characteristics, not tested in production. 5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 78). This data is based on characterization results, tested in production at VDD max. 6. Data based on characterization results, not tested in production. 7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
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I/O PORT PIN CHARACTERISTICS (Cont'd) 13.8.2 Output Driving Current Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 79 and Figure 82) VOL
1)
Conditions IIO=+5mA TA85C TA85C IIO=+2mA TA85C TA85C VDD=5V IIO=+20mA, TA85C TA85C IIO=+8mA TA85C TA85C
Min
Max 1.3 1.5 0.65 0.75 1.5 1.7 0.75 0.85
Unit
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 80 and Figure 83) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 81 and Figure 84)
V
VOH
2)
IIO=-5mA, TA85C VDD-1.6 TA85C VDD-1.7 IIO=-2mA TA85C VDD-0.8 TA85C VDD-1.0
Figure 79. Typical VOL at VDD=5V (standard)
Vol [V] at Vdd=5V 2.5 Ta=-40C 2 1.5 1 0.5 0 0 2 4 Iio [mA] 6 8 10 Ta=25C Ta=125C Ta=85C
Figure 81. Typical VOH at VDD=5V
Voh [V] at Vdd=5V 6 5 4 3 2 1 -8 -6 -4 Iio [mA] -2 0 Ta=-40C Ta=25C Ta=85C Ta=125C
Figure 80. Typical VOL at VDD=5V (high-sink)
Vol [V] at Vdd=5V 2 Ta=-40C 1.5 Ta=25C 1 0.5 0 0 5 10 15 Iio [mA] 20 25 30 Ta=125C Ta=85C
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 82. Typical VOL vs. VDD (standard I/Os)
Vol [V] at Iio=2mA 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40C Ta=25C Ta=85C Ta=125C Vol [V] at Iio=5mA 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 3.2 3.5 4 Ta=-40C Ta=25C Ta=85C Ta=125C
4.5 Vdd [V]
5
5.5
Figure 83. Typical VOL vs. VDD (high-sink I/Os)
Vol [V] at Iio=8mA 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 5.5 Vdd [V] 0.7 0.5 3.2 3.5 4 4.5 5 5.5 Vdd [V] 1.1 0.9 Ta=25C Ta=125C 1.3 Ta=-40C Ta=85C Vol [V] at Iio=20mA 1.5 Ta=25C Ta=125C Ta=-40C Ta=85C
Figure 84. Typical VOH vs. VDD
Voh [V] at Iio=-2mA 5.5 5 4.5 4 3.5 3 2.5 2 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=25C Ta=125C 1 0 3.5 4 4.5 Vdd [V] 5 5.5 Ta=-40C Ta=85C 3 2 Ta=-40C Ta=25C Ta=85C Ta=125C Voh [V] at Iio=-5mA 5 4
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13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys VOL RON Parameter Input low level voltage
2)
Conditions
Min 0.7xVDD
Typ 1)
Max 0.3xVDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Output low level voltage (see Figure 87, Figure 88) Weak pull-up equivalent resistor 5)
4)
400 VDD=5V VIN=VSS IIO=+5mA IIO=+2mA VDD=5V VDD=3.4V 20 80 0.68 0.28 40 100 6 30 20 100 0.95 0.45 60 120
V k 1/fSFOSC s s ns
tw(RSTL)out Generated reset pulse duration th(RSTL)in tg(RSTL)in External reset pulse hold time 6) Filtered glitch duration 7)
External pin or internal reset sources
Figure 85. Typical Application with RESET pin 8)
AL
VDD ST72XXX
PT
IO
VDD
VDD RON
N
USER EXTERNAL RESET CIRCUIT 8)
0.1F
4.7k RESET
INTERNAL RESET CONTROL
O
0.1F
WATCHDOG RESET LVD RESET
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics described in Figure 86). This data is based on characterization results, not tested in production. 6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environments. 8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
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CONTROL PIN CHARACTERISTICS (Cont'd) Figure 86. Typical ION vs. VDD with VIN=VSS
Ion [A] 200 150 100 50 0 3.2 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40C Ta=25C Ta=85C Ta=125C
Figure 87. Typical VOL at VDD=5V (RESET)
Vol [V] at Vdd=5V 2 Ta=25C 1.5 1 0.5 0 0 1 2 3 4 Iio [mA] 5 6 7 8 Ta=125C Ta=-40C Ta=85C
Figure 88. Typical VOL vs. VDD (RESET)
Vol [V] at Iio=2mA 0.5 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 4.5 5 5.5 Vdd [V]
0.6 0.4 3.2 3.5 4 4.5 5 5.5 Vdd [V]
Ta=-40C Ta=25C
Ta=85C Ta=125C
Vol [V] at Iio=5mA 1.2 1 0.8
Ta=-40C Ta=25C
Ta=85C Ta=125C
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CONTROL PIN CHARACTERISTICS (Cont'd) 13.9.2 ISPSEL Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH IL Parameter Input low level voltage 1) Input high level voltage 1) Input leakage current Conditions Min VSS VDD-0.1 Max 0.2 12.6 1 Unit V A
VIN=VSS
Figure 89. Two typical Applications with ISPSEL Pin 2)
ISPSEL
PROGRAMMING TOOL 10k
ISPSEL
ST72XXX
ST72XXX
Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS.
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13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 13.10.1 Watchdog Timer
Symbol tw(WDG) Parameter Watchdog time-out duration Conditions fCPU=8MHz Min 12,288 1.54 Typ Max 786,432 98.3 Unit tCPU ms
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
13.10.2 16-Bit Timer
Symbol Parameter Conditions Min 1 2 fCPU=8MHz 250 0 0 fCPU/4 fCPU/4 16 Typ Max Unit tCPU tCPU ns MHz MHz bit tw(ICAP)in Input capture pulse time tres(PWM) PWM resolution time fEXT fPWM Timer external clock frequency PWM repetition rate
ResPWM PWM resolution
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13.11 COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter SPI clock frequency
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit MHz
Conditions Master fCPU=8MHz Slave fCPU=8MHz
SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge)
see I/O port pin description 120 120 100 90 100 100 100 100 0
ns 120 240 120
0 0.25 0.25
tCPU
Figure 90. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterization results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 91. SPI Slave Timing Diagram with CPHA=1 1)
SS INPUT tsu(SS) SCK INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 92. SPI Master Timing Diagram 1)
SS INPUT tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT
see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 13.11.2 I2C - Inter IC Control Interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table.
Standard mode I2C Min 1) 4.7 4.0 250 0 3) 1000 300 4.0 4.7 4.0 4.7 400 Max 1) Fast mode I2C Min 1) 1.3 0.6 100 0 2) 20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3 400 900 3) 300 300 s ns ms pF ns Max 1) Unit s
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time
Parameter
SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line
tw(STO:STA) STOP to START condition time (bus free)
Figure 93. Typical Application with I2C Bus and Timing Diagram 4)
VDD 4.7k I2 C BUS 4.7k VDD 100 100 SDAI SCLI
ST72XXX
REPEATED START START
tsu(STA)
SDA
tw(STO:STA)
START
tf(SDA)
SCK
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol fADC VAIN RAIN CADC tSTAB tADC Parameter ADC clock frequency Conversion range voltage 2) External input resistor Internal sample and hold capacitor Stabilization time after ADC enable Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time fCPU=8MHz, fADC=4MHz 6 0
4)
Conditions
Min VSSA
Typ 1)
Max 4 VDDA 10
3)
Unit MHz V k pF s 1/fADC
3 4 8
Figure 94. Typical Application with ADC
VDD VT 0.6V RAIN VAIN CIO ~2pF VDD VDDA 0.1F VSSA VT 0.6V IL 1A AINx
ADC
ST72XXX
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid.
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8-BIT ADC CHARACTERISTICS (Cont'd) ADC Accuracy
Symbol |ET| EO EG |ED| |EL| Parameter Total unadjusted error 1) Offset error
1)
VDD=5V, 2) fCPU=1MHz Min Max 2.0 1.5 1.5
VDD=5.0V, 3) fCPU=8MHz Min Max 2.0 1.5 1.5 1.5 1.5
VDD=3.3V, 3) fCPU=8MHz Min Max 2.0 1.5 1.5 1.5 1.5
Unit
Gain Error 1) Differential linearity error Integral linearity error
1) 1)
LSB
1.5 1.5
Figure 95. ADC Accuracy Characteristics
Digital Result ADCDR 255 254 253 1LSB IDEAL V -V DDA SSA = ---------------------------------------256 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL Vin (LSBIDEAL) 5 6 7 253 254 255 256 VDDA EO EL ED (3) (1) EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Notes: 1. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB for each 10K increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 2. Data based on characterization results with TA=25C. 3. Data based on characterization results over the whole temperature range.
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14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA Figure 96. 28-Pin Plastic Small Outline Package, 300-mil Width
Dim. A A1 B C D E e H h K L G SO28 N
mm Min 2.35 0.10 0.33 0.23 17.70 7.40 1.27 10.01 0.25 0.41 10.64 0.394 0.74 0.010 0 1.27 0.016 0.10 Typ Max Min 2.65 0.0926 0.30 0.0040 0.51 0.013 0.32 0.0091 18.10 0.6969 7.60 0.2914
inches Typ Max 0.1043 0.0118 0.020 0.0125 0.7125 0.2992 0.0500 0.419 0.029 8 0.050 0.004 28
Number of Pins
14.2 ECOPACK(R) In accordance with the RoHS European directive, all STMicroelectronics packages have been converted to lead-free technology, named ECOPACK(R). - ECOPACK(R) packages are qualified according to the JEDEC STD-020B compliant soldering profile. 14.3 THERMAL CHARACTERISTICS
Symbol RthJA PD TJmax Power dissipation 1) Maximum junction temperature
2)
- Detailed information on the STMicroelectronics ECOPACK(R) transition program is available on www.st.com/stonline/leadfree/, with specific technical application notes covering the main technical aspects related to lead-free conversion (AN2033, AN2034, AN2035 and AN2036).
Ratings Package thermal resistance (junction to ambient) SO28
Value 75 500 150
Unit C/W mW C
Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
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15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM). Flash devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. 15.1 OPTION BYTES The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the Flash is fixed to FFh. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). USER OPTION BYTE 0 Bit 7:2 = Reserved, must always be 1. Bit 1 = EXTIT External Interrupt Configuration. This option bit allows the external interrupt mapping to be configured as shown in Table 23. Table 23. External Interrupt Configuration
External IT0 Ports PA7-PA0 Ports PA7-PA0 Ports PC5-PC0 External IT1 Ports PB7-PB0 Ports PC5-PC0 Ports PB7-PB0 EXTIT 1 0
USER OPTION BYTE 1 Bit 7 = CFC Clock filter control on/off This option bit enables or disables the clock filter (CF) features. 0: Clock filter enabled 1: Clock filter disabled Bit 6:4 = OSC[2:0] Oscillator selection These three option bits can be used to select the main oscillator as shown in Table 24. Bit 3:2 = LVD[1:0] Low voltage detection selection These option bits enable the LVD block with a selected threshold as shown in Table 25. Bit 1 = WDG HALT Watchdog and halt mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Bit 0 = WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Table 24. Main Oscillator Configuration
Selected Oscillator External Clock (Standby) ~4 MHz Internal RC 1~14 MHz External RC Low Power Resonator (LP) Medium Power Resonator (MP) Medium Speed Resonator (MS) High Speed Resonator (HS) OSC2 OSC1 OSC0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 X 1 0 1 0
Table 25. LVD Threshold Configuration
Configuration LVD Off Highest Voltage Threshold (4.50V) Medium Voltage Threshold (4.05V) Lowest Voltage Threshold (3.45V) LVD1 LVD0 1 1 0 0 1 0 1 0
Bit 0 = FMP Full memory protection. This option bit enables or disables external access to the internal program memory (readout protection). Clearing this bit causes the erasing (by overwriting with the currently latched values) of the whole memory (not including the option bytes). 0: Program memory not readout protected 1: Program memory readout protected
USER OPTION BYTE 0 7 Reserved Default Value 1 1 1 1 1 1 0
USER OPTION BYTE 1 7 0 OSC OSC OSC WDG WDG LVD1 LVD0 2 1 0 HALT SW 1 1 0 1 1 1 1
EXTIT FMP CFC 1 0 1
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15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Figure 97. ROM Factory Coded Device Types The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
DEVICE PACKAGE TEMP. RANGE / XXX Code name (defined by STMicroelectronics) A = -40 to +85C B = -40 to +105C C = -40 to +125C M = Plastic SOIC ST72104G1, ST72104G2, ST72215G2, ST72216G1, ST72254G1, ST72254G2
Figure 98. Flash User Programmable Device Types
DEVICE PACKAGE TEMP. RANGE
A = -40 to +85C B = -40 to +105C C = -40 to +125C M = Plastic SOIC ST72C104G1, ST72C104G2, ST72C215G2, ST72C216G1, ST72C254G1, ST72C254G2
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TRANSFER OF CUSTOMER CODE (Cont'd)
MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference Device: Package: Marking: ..................................................................... ..................................................................... ..................................................................... ..................................................................... ..................................................................... ..................................................................... [ ] ST72104G1 (4KB) [ ] ST72104G2 (8KB) [ ] SO28 [ ] ST72215G2 (4KB) [ ] ST72216G1 (8KB) [ ] Tape & Reel [ ] ST72254G1 (4KB) [ ] ST72254G2 (8KB) [ ] Tube
[ ] Standard Marking [ ] Special Marking SO28 (max. 13 Chars.): _____________ Authorized characters are letters, digits, `.', `-', `/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. [ ] IT0 interrupt vector Port A, IT1 interrupt vector Port B & C [ ] IT0 interrupt vector Port A & C, IT1 interrupt vector Port B [ ] -40C to +85C [ ] Resonator: [ ] -40C to +105C [ ] -40C to +125C
External Interrupt:
Temperature Range: Clock Source Selection:
[ ] RC Network: [ ] External Clock Clock Security System: Watchdog Selection: Halt when Watchdog on: Readout Protection: LVD Reset [ ] Disabled [ ] Software Activation [ ] Reset [ ] Disabled [ ] Disabled
[ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] Internal [ ] External
[ ] Enabled [ ] Hardware Activation [ ] No reset [ ] Enabled [ ] Enabled: [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold
Comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes: Signature: .......................................................................... ..........................................................................
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15.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site. Third Party Tools ACTUM BP COSMIC CMX DATA I/O HITEX HIWARE ISYSTEM KANDA LEAP Tools from these manufacturers include C compliers, emulators and gang programmers. Table 26. STMicroelectronics Tool Features
Tool ST7 Development Kit In-Circuit Emulation Programming Capability1) Yes. (Same features as HDS2 emulator but without Yes (DIP packages only)2) logic analyzer) Yes, powerful emulation No features including trace/ logic analyzer No Yes (All packages) Software Included ST7 CD ROM with: - ST7 Assembly toolchain - STVD7 and WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT - C compiler demo versions - ST Realizer for Win 3.1 and Win95 - Windows Programming Tools for Win 3.1, Win 95 and NT
STMicroelectronics Tools Three types of development tool are offered by ST; all of them connect to a PC via a parallel (LPT) port (see Table 26 and Table 27 for more details).
ST7 HDS2 Emulator
ST7 Programming Board
Notes: 1. In-Situ Programming (ISP) interface for Flash devices. 2. Tool equipped with a DIP socket only; an adapter may be required to program devices in SO packages.
Table 27. Dedicated STMicroelectronics Development Tools
Supported Products ST72254G1, ST72C254G1 ST72254G2, ST72C254G2 ST72215G2, ST72C215G2 ST72216G1, ST72C216G1 ST72104G1, ST72C104G1, ST72104G2, ST72C104G2 ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board ST7MDT1-EPB2/EU ST7MDT1-DVP2 ST7MDT1-EMU2B ST7MDT1-EPB2/US ST7MDT1-EPB2/UK
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DEVELOPMENT TOOLS (Cont'd) 15.3.1 Package/Socket Footprint Proposal Table 28. Suggested List of SO28 Socket Types
Package / Probe SO28 EMU PROBE ENPLAS YAMAICHI Adaptor / Socket Reference OTS-28-1.27-04 IC51-0282-334-1 X Same Footprint Socket Type Open Top Clamshell SMD to SDIP
Adapter from SO28 to SDIP32 footprint (delivered with emulator)
15.4 ST7 APPLICATION NOTES All relevant ST7 application notes can be found on www.st.com.
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16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Date Rev. Main changes Initial release of the ST72104Gx-Auto, ST72215GX-AUTO, ST72216Gx-Auto, ST72254Gx-Auto datasheet The ST72xxxG-Auto datasheet was created from the ST72104G, ST72215G, ST72216G, ST72254G Preliminary Data datasheet, revision 2.6 dated November 2000, with the following changes: Changed document title and description on page 1 Removed SDIP32 package outline from page 1 "Device Summary" on page 1: - changed operating temperature range - removed SDIP32 package Section 1 "INTRODUCTION" on page 6: Added `-Auto' extension to ST72xxxG numbers in first paragraph Section 2 "PIN DESCRIPTION" on page 7: Removed Figure "32-Pin SDIP Package Pinout" Table 1 on page 8: Removed SDIP32 pin number column Section 6 "SUPPLY, RESET AND CLOCK MANAGEMENT" on page 17: Added `-Auto' extension to ST72xxxG numbers in first paragraph "MULTI-OSCILLATOR (MO)" on page 21: Modified description of external and internal RC Section 11.1.3 "Functional Description" on page 39: Replaced 500ns with 30s at end of second paragraph to be in line with spec given in Section 13.9.1 "Asynchronous RESET Pin" on page 119 Section 12.1.4 "Indexed (No Offset, Short, Long)" on page 90: Replaced "The indirect addressing mode consists of" with "The indexed addressing mode consists of" in second paragraph Section 13.2.1 "Voltage Characteristics" on page 96: Changed VIN ratings and values Section 13.3.1 "General Operating Conditions" on page 97: Modified ambient temperature range conditions to include only automotive device suffix versions Section 13.5.3.2 "Typical Ceramic Resonators" on page 106: Removed Table "Typical Ceramic Resonators for General Purpose Applications" Changed titles of Figure 81 on page 117 and Figure 84 on page 118 Figure 91.SPI Slave Timing Diagram with CPHA=1 1): Corrected `CPHA=0' to read `CPHA=1' for SCKINPUT Section 14.1 "PACKAGE MECHANICAL DATA" on page 128: - removed Figure "32-Pin Shrink Plastic Dual In Line Package" - added Section 14.2 "ECOPACK(R)" on page 128 - removed Section "SOLDERING AND GLUEABILITY INFORMATION" Section 14.3 "THERMAL CHARACTERISTICS" on page 128: Removed SDIP32 package from package thermal resistance ratings Figure 97.ROM Factory Coded Device Types: Modified to include only automotive device temperature versions and removed DIP package Figure 98.Flash User Programmable Device Types: Modified to include only automotive device temperature versions and removed DIP package Section 15.1 "OPTION BYTES" on page 129: Changed description of FMP option bit "MICROCONTROLLER OPTION LIST" on page 131: Modified to include only automotive device temperature versions and removed DIP package Section 15.3 "DEVELOPMENT TOOLS" on page 132: Removed link `http//mcu.st.com' from the end of the first paragraph Table 26, "STMicroelectronics Tool Features," on page 132: Added footnote 2 Section 15.3.1 "Package/Socket Footprint Proposal" on page 133: Removed Table "Suggested List of SDIP32 Socket Types" Section 15.4 "ST7 APPLICATION NOTES" on page 133: Removed Table "ST7 Application Notes" Updated disclaimer on last page to include a mention about the use of ST products in automotive applications
29-Oct-2007
1
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